NLTL-6273CH

NLTL-6273 belongs to Marki Microwave’s NLTL family of multipliers and non-linear transmission lines. The NLTL product line consists of passive GaAs MMIC non-linear transmission lines designed and fabricated with GaAs Schottky diode based varactors. NLTLs take an input signal and create an impulse train of harmonics. Harmonic outputs up to and beyond 40 GHz are generated by the NLTL. The NLTL-6273SM is the packaged 5 mm QFN version of the NLTL-6273CH.

Port 1 supports L and S band input signals. Port 2 will output integer multiples of the input signal (i.e., x2, x3, x4, …, x30) up to the 30th output harmonic or a maximum of 40 GHz. Higher harmonics can be generated but will be at a lower efficiency.

The operating conditions of the NLTL are extremely important to optimize performance. High power inputs will increase the output power observed; however, the conversion efficiency will decrease. This is increasingly true for higher input frequencies and at input powers above the recommended limit. Optimal conversion efficiency of the NLTL is achieved using a square wave input with a fast rise time. Doing so causes a degradation in the 2nd output harmonic but otherwise improves the conversion efficiency at all other harmonics.

NLTL-6273 requires no external DC bias. The self-bias of the diodes caused by the rectified RF input signal is sufficient for operation. For the best performance, optimization of the DC return path is recommended for each specific application to optimize the harmonic output power distribution.

The phase noise of a non-linear transmission line is outstanding. If verification of performance is necessary, the application circuit used and input conditions are extremely important. NLTLs are AM sensitive. If there is excessive AM noise on the input of the NLTL, observing the output of the NLTL will show excessive PM/phase noise because of the high AM to PM conversion property of NLTLs.

DC Path to Ground — An RF choke followed by a 15 Ω resistor should be used to provide a DC path to ground on the input port of the NLTL. A shunt 1 μF capacitor is used to filter noise generated by the resistor. This forms the circuit which self-biases the NLTL. The DC return to ground removes DC rectified current created by high power RF signal injection. The DC path to ground is provided within the S package. A conical coil inductor is recommended to push the self-resonance frequency of the inductor past the operating bandwidth of the NLTL. The recommended inductance value of the conical coil inductor is 50nH or higher.

Blocking Capacitor — A DC blocking capacitor on the output of the NLTL-6273’s integrated circuit is necessary to prevent unwanted DC current flow from or to the output. If there is a DC signal on the input, place a DC block on the input to avoid disrupting the self-biasing of the diodes.

Marki MMICs should be attached directly to a ground plane with conductive epoxy. The ground plane electrical impedance should be as low as practically possible. This will prevent resonances and permit the best possible electrical performance. Datasheet performance is only guaranteed in an environment with a low electrical impedance ground.

Mounting - To epoxy the chip, apply a minimum amount of conductive epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip. Cure epoxy according to manufacturer instructions.

Wire Bonding - Ball or wedge bond with 0.025 mm (1 mil) diameter pure gold wire. Thermosonic wirebonding with a nominal stage temperature of 150 °C and a ball bonding force of 40 to 50 grams or wedge bonding force of 18 to 22 grams is recommended. Use the minimum level of ultrasonic energy to achieve reliable wirebonds. Wirebonds should be started on the chip and terminated on the package or substrate. All bonds should be as short as possible <0.31 mm (12 mils).

Circuit Considerations – 50 Ω transmission lines should be used for all high frequency connections in and out of the chip. Wirebonds should be kept as short as possible, with multiple wirebonds recommended for higher frequency connections to reduce parasitic inductance. In circumstances where the chip more than .001” thinner than the substrate, a heat spreading spacer tab is optional to further reduce bondwire length and parasitic inductance.

Handling Precautions

General Handling

Chips should be handled with care using tweezers or a vacuum collet. Users should take precautions to protect chips from direct human contact that can deposit contaminants, like perspiration and skin oils on any of the chip's surfaces.

Static Sensitivity

GaAs MMIC devices are sensitive to ESD and should be handled, assembled, tested, and transported only in static protected environments.

Cleaning and Storage: Do not attempt to clean the chip with a liquid cleaning system or expose the bare chips to liquid. Once the ESD sensitive bags the chips are stored in are opened, chips should be stored in a dry nitrogen atmosphere.

Bonding Diagram